Senior Lead Engineer

Company: ACL Digital
Location: San Jose
Posted on: November 13, 2024

Job Description:

Minimum Requirements:

• Requires Bachelor's degree or its equivalent in the field(s) of Electronics and Telecommunications or related field.Location:
  • Calsoft Labs Inc., d/b/a ACL Digital - 2890 Zanker Road, Suite 200, San Jose, CA 95134Experience:
    • BS 5 + years
    • Knowledge of verification methodology involving OOPs concepts C++, OVM/UVM.
    • Design and verification flows. Experience in developing complex test bench/model in Verilog, System Verilog or C/C++.
    • Experience in verifying design at system level, and Memory management system with Cache Coherency.
    • Experience with on full-chip or sub-system verification. Good understanding of ASIC Design Flow and SOC architecture, digital design, verification lifecycle, tools and methodologies.
    • Preparing comprehensive test plan based on the specification & interactions with Architecture & RTL teams.
    • Knowledge of Constraint-Random, coverage-driven verification environments development in System Verilog / C ++ (drivers / monitors, constraint random tests, checkers and self-checking models and coverage models written in System Verilog-Covergroup / SVA)
    • Knowledge of simulation tools and coverage database visualization tools.
    • Understand design verification (IP level). Must have an experience in driving/leading verification tasks.
    • Experience with coverage-based verification methodology. Experience in random test generation, coverage analysis, failure debug.
    • Develop, document and execute RTL verification test plans.
    • Experience with constrained-random, coverage-driven automated verification using module-to-system level reuse methodology (e.g. UVM, OVM, VMM, eRM), using hardware verification languages such as SystemVerilog.
    • Experience using scripting (Perl, Python and Makefile) to automate tool flows and report generation.
    • Experience in both hardware verification and software verification - using RTL/FPGA/Emulation platforms would be a plus.
    • Experience verifying any of embedded CPU-Subsystems, AMBA Bus protocols, PCIe, and Network-on-Chip.
    • Familiar with Linux Environment (including shell scripting and Linux GNU tools).Gate Level Simulations:
      • Define and implement the flow for execution of GLS.
      • Work with Design/RTL teams to understand the different blocks to execute. Each block could be using different libraries.
      • Understand the RTL simulation environment of the project. Work with verification teams to define the test cases to run and verify the design at gate level.Additional Skills:
        • Strong debug skills and demonstrated experience in Tcl and Perl scripting.
        • Expertise in generating structural test patterns and analyzing and improving coverage.
        • Excellent in multi-tasking & work on several high priority designs in parallel. Experience in writing test plans and test cases.
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Keywords: ACL Digital, San Francisco , Senior Lead Engineer, Engineering , San Jose, California