Staff SERDES Verification Engineer

Company: Synopsys, Inc.
Location: Sunnyvale
Posted on: April 7, 2025

Job Description:

We Are:At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.You Are:You are a highly motivated ASIC Digital Design Engineer with a passion for pushing the boundaries of technology. With a strong background in interface protocols such as Ethernet, PCIe, CXL, JESD, and CPRI, you excel in functional verification flows and methodologies, particularly VMM, OVM/UVM, and System Verilog. Your expertise in Gate Level Simulation with SDF, System Verilog Assertions, and coverage implementation sets you apart. You possess fundamental knowledge of Analog and Digital mixed signal design, and your scripting skills in TCL/Perl/Python are top-notch. You are a team player with excellent communication skills, problem-solving abilities, and interpersonal skills, eager to deliver high-quality RTL and Simulation models to customers and support them through silicon bring-up and debug processes.What You'll Be Doing:

• Develop and review the verification test-plan for multi-protocol 112G PHY IP (Serdes).
• Create and optimize the verification environment based on UVM.
• Execute RTL simulations, Gate Level Simulations, and ensure coverage closure (Functional + Code).
• Deliver high-quality RTL and Simulation models to customers.
• Coordinate between RTL, Analog design, and Tech pub teams.
• Support customers with the integration and bring-up of IP in their simulation environments.
• Develop and deliver SV verification components for customer integration.
• Assist customers with silicon bring-up and debug issues when customer silicon is available.The Impact You Will Have:
  • Ensure the delivery of robust and high-quality verification solutions for Synopsys' high-performance PHY IPs.
  • Drive innovation and efficiency in verification processes, contributing to the advancement of cutting-edge technologies.
  • Enhance customer satisfaction through exceptional support and high-quality deliverables.
  • Facilitate the seamless integration of Synopsys IPs into customer designs, ensuring successful product launches.
  • Contribute to the development of industry-leading verification methodologies and best practices.
  • Help maintain Synopsys' reputation as a leader in chip design and verification solutions.What You'll Need:
    • B.Tech/M.Tech with 7+ years of relevant experience.
    • Proficiency in interface protocols such as Ethernet, PCIe, CXL, JESD, and CPRI.
    • Experience with functional verification flow, Verification tools, and methodologies VMM, OVM/UVM, and System Verilog.
    • Expertise in Gate Level Simulation with SDF, System Verilog Assertions, and coverage implementation.
    • Fundamental knowledge of Analog and Digital mixed signal design.
    • Proficiency in scripting and automation using TCL/Perl/Python.
    • Excellent debug and diagnostic skills.Who You Are:You are an innovative and detail-oriented professional with a strong technical background and a collaborative mindset. Your excellent communication skills, problem-solving abilities, and interpersonal skills make you a valuable team player. You thrive in a dynamic environment, continually seeking to improve processes and deliver high-quality results. Your passion for technology and dedication to customer success drive you to excel in your role.The Team You'll Be A Part Of:You will join a dynamic and collaborative team focused on the verification of high-performance multi-protocol PHY IPs. Our team is dedicated to delivering innovative solutions and exceptional support to our customers, ensuring the successful integration and deployment of Synopsys IPs. Together, we drive technological advancements and set industry standards in chip design and verification.Rewards and Benefits:We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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Keywords: Synopsys, Inc., San Francisco , Staff SERDES Verification Engineer, Engineering , Sunnyvale, California